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upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6210-ds-p0000 UP6210 1 preliminary compact dual-phase synchronous-rectified buck controller the UP6210 is a compact dual-phase synchronous-rectified buck controller specifically designed to deliver high quality output voltage for high power applications. this part is capable of delivering up to 60a output current thanks to its embedded bootstrapped drivers that support 12v + 12v driving capability. the UP6210 features configurable gate driving voltage for maximum efficiency and optimal performance. the built-in bootstrap diode simplifies the circuit design and reduces external part count and pcb space. the output voltage is precisely regulated to the reference input that is dynamically adjustable by external voltage divider. the UP6210 adopts dcr current sensing technique for over current protection and droop control. the adjustable current balance is achieved by r ds(on) current sensing technique. this part features comprehensive protection functions including over current protection, input/output under voltage protection, over voltage protection and over temperature protection. other features include adjustable soft start, adjustable operation frequency, and quick response to step load transient. with aforementioned functions, this part provides customers a compact, high efficiency, well-protected and cost-effective solutions. this part comes to vqfn4x4-24l package. ? ? ? ? ? middle-high end gpu core power ? ? ? ? ? high end desktop pc memory core power ? ? ? ? ? low output voltage, high power density dc-dc converters ? ? ? ? ? voltage regulator modules ? ? ? ? ? operate with single supply voltage ? ? ? ? ? 2.0% over line voltage and temperature ? ? ? ? ? simple single-loop voltage-mode control ? ? ? ? ? 12v bootstrapped drivers with internal bootstrap diode ? ? ? ? ? adjustable over current protection by dcr current sensing ? ? ? ? ? adjustable current balancing by r ds(on) current sensing ? ? ? ? ? adjustable operation frequency form 50khz to 1mhz per phase ? ? ? ? ? external compensation ? ? ? ? ? dynamic output voltage adjustment ? ? ? ? ? adjustable soft start ? ? ? ? ? vqfn4x4-24l package ? ? ? ? ? rohs compliant and 100% lead (pb)-free r e b m u n r e d r oe p y t e g a k c a pk r a m e r g a q a 0 1 2 6 p ul 4 2 - 4 x 4 n f q v general description a pplications ordering information features pin configuration note: upi products are compatible with the current ipc/ jedec j-std-020 and rohs requirements. they are 100% matte tin (sn) plating and suitable for use in snpb or pb- free soldering processes. vqfn4x4-24l boot2 4 3 2 1 lg1 hg1 rt/en vid csn fb vref hg2 sw2 gnd 10 9 8 7 21 22 23 24 17 16 15 18 5 sw1 11 ss 14 20 vcc 6 12 13 19 csp refin comp pvcc psi eap iofs rset lg2 boot1 fbrtn
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6210-ds-p0000 UP6210 2 preliminary typical application circuit q 1 UP6210 vcc csp csn ph1 ph2 psi vref iofs refin fb comp fbrtn pvcc eap rt/en ss gnd v in v out v out rset vid fbrtn boot1 hg1 sw1 lg1 boot2 hg2 sw2 lg2
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6210-ds-p0000 UP6210 3 preliminary . o ne m a n n i pn o i t c n u f n i p 1n i f e r . t u p n i e c n e r e f e r l a n r e t x e r e d i v i d e g a t l o v a t c e n n o c . e g a t l o v e c n e r e f e r l a n r e t x e f o n i p t u p n i s i s i h t . e g a t l o v e c n e r e f e r e h t t e s o t n t r b f o t n i f e r o t f e r v m o r f 2f e r v . e g a t l o v e c n e r e f e r r o f t u p t u o . e g a t l o v e c n e r e f e r v 2 n o i s i c e r p h g i h f o n i p t u p t u o e h t s i s i h t . n t r b f o t r o t i c a p a c c i m a r e c f u 1 a h t i w n i p s i h t s s a p y b 3n e / t r . g n i t t e s y c n e u q e r f n o i t a r e p o e h t t e s o t d n g d n a n i p s i h t n e e w t e b r o t s i s e r a g n i t c e n n o c . 0 1 2 6 p u e h t n w o d t u h s o t d n u o r g o t n i p s i h t l l u p . y c n e u q e r f n o i t a r e p o 4s f o i . t n e m t s u j d a e c n a l a b t n e r r u c e h t t s u j d a o t d n g r o f e r v o t n i p s i h t m o r f r o t s i s e r a t c e n n o c . g n i r a h s t n e r r u c 5p m o c . t u p t u o r e i f i l p m a r o r r e f o t u p n i g n i t r e v n i - n o n e h t d n a ) a e ( r e i f i l p m a r o r r e e h t f o t u p t u o e h t s i s i h t - e g a t l o v e h t e t a s n e p m o c o t n i p b f e h t h t i w n o i t a n i b m o c n i n i p s i h t e s u . s r o t a r a p m o c m w p e h t . r e t r e v n o c e h t f o p o o l k c a b d e e f l o r t n o c 6b f . e g a t l o v k c a b d e e f n o i t a n i b m o c n i n i p s i h t e s u . r e i f i l p m a r o r r e e h t o t t u p n i g n i t r e v n i e h t s i n i p s i h t . r e t r e v n o c e h t f o p o o l k c a b d e e f l o r t n o c e g a t l o v e h t e t a s n e p m o c o t n i p p m o c e h t h t i w 7n t r b f . n r u t e r k c a b d e e f . d e t a l u g e r e b o t s i e g a t l o v t u p t u o e h t e r e h w n i p d n u o g e h t o t n i p s i h t t c e n n o c 8p a e . r e i f i l p m a r o r r e f o t u p n i g n i t r e v n i - n o n . e p o l s p o o r d e h t t e s o t n i p s s o t r o t s i s e r a t c e n n o c 9s s . t u p t u o t r a t s t f o s . l a v r e t n i t r a t s t f o s e h t t e s o t n t r b f o t r o t i c a p a c a t c e n n o c 0 1n s c . r e i f i l p m a g n i s n e s t n e r r u c r o f t u p n i e v i t a g e n 1 1p s c . r e i f i l p m a g n i s n e s t n e r r u c r o f t u p n i e v i t i s o p 2 1i s p . e d o m g n i v a s r e w o p d l o h s e r h t e d o m g n i v a s r e w o p e h t t e s o t d n g o t i s p m o r f r o t s i s e r a t c e n n o c r o f d n u o r g o t n i p s i h t t r o h s . n o i t a r e p o e s a h p o w t s y a w l a r o f f e r v o t n i p s i h t t c e n n o c . l e v e l t n e r r u c . n o i t a r e p o e s a h p e l g n i s s y a w l a 3 11 t o o b y l p p u s p a r t s t o o b r o t i c a p a c p a r t s t o o b e h t t c e n n o c . 1 l e n n a h c f o r e v i r d e t a g r e p p u g n i t a o l f e h t r o f c t o o b . t i u c r i c p a r t s t o o b a m r o f o t n i p 1 w s e h t d n a n i p 1 t o o b n e e w t e b 4 11 g h . 1 l e n n a h c r o f t u p t u o r e v i r d e t a g r e p p u s i h t . t e f s o m r e p p u f o e t a g e h t o t n i p s i h t t c e n n o c r e p p u e h t n e h w e n i m r e t e d o t y r t i u c r i c n o i t c e t o r p h g u o r h t - t o o h s e v i t p a d a e h t y b d e r o t i n o m s i n i p . f f o d e n r u t s a h t e f s o m 5 11 w s . 1 l e n n a h c r o f e d o n h c t i w s n i a r d e h t d n a t e f s o m r e p p u e h t f o e c r u o s e h t o t n i p s i h t t c e n n o c d e r o t i n o m o s l a s i n i p s i h t . r e v i r d e t a g u e h t r o f k n i s e h t s a d e s u s i n i p s i h t . t e f s o m r e w o l e h t f o d e n r u t s a h t e f s o m r e p p u e h t n e h w e n i m r e t e d o t y r t i u c r i c n o i t c e t o r p h g u o r h t - t o o h s e v i t p a d a e h t y b . f f o 6 11 g l . 1 l e n n a h c r o f t u p t u o r e v i r d e t a g r e w o l s i h t . t e f s o m r e w o l f o e t a g e h t o t n i p s i h t t c e n n o c r e w o l e h t n e h w e n i m r e t e d o t y r t i u c r i c n o i t c e t o r p h g u o r h t - t o o h s e v i t p a d a e h t y b d e r o t i n o m s i n i p . f f o d e n r u t s a h t e f s o m 7 1c c v p . r e v i r d e t a g r o f e g a t l o v y l p p u s t n e r r u c s e d i v o r p n i p s i h t . o d l v 9 l a n r e t n i f o t u p t u o e h t s i n i p s i h t . r o t i c a p a c c i m a r e c f u 1 m u m i n i m a h t i w n i p s i h t s s a p y b . s e v i r d e t a g r o f 8 1c c v . e g a t l o v y l p p u s n i p s i h t e s s a p y b . o d l v 9 d n a t i u c r i c l o r t n o c l a n r e t n i r o f t n e r r u c s e d i v o r p n i p s i h t . c i e h t o t t x e n r o t i c a p a c c i m a r e c f u 1 m u m i n i m a h t i w functional pin descriptio n
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6210-ds-p0000 UP6210 4 preliminary functional block diagram . o ne m a n n i pn o i t c n u f n i p 9 12 g l . 2 l e n n a h c r o f t u p t u o r e v i r d e t a g r e w o l s i h t . t e f s o m r e w o l f o e t a g e h t o t n i p s i h t t c e n n o c r e w o l e h t n e h w e n i m r e t e d o t y r t i u c r i c n o i t c e t o r p h g u o r h t - t o o h s e v i t p a d a e h t y b d e r o t i n o m s i n i p . f f o d e n r u t s a h t e f s o m 0 22 w s . 2 l e n n a h c r o f e d o n h c t i w s e h t d n a t e f s o m r e p p u e h t f o e c r u o s e h t o t n i p s i h t t c e n n o c o s l a s i n i p s i h t . r e v i r d 2 g h e h t r o f k n i s e h t s a d e s u s i n i p s i h t . t e f s o m r e w o l e h t f o n i a r d r e p p u e h t n e h w e n i m r e t e d o t y r t i u c r i c n o i t c e t o r p h g u o r h t - t o o h s e v i t p a d a e h t y b d e r o t i n o m . f f o d e n r u t s a h t e f s o m 1 22 g h . 2 l e n n a h c r o f t u p t u o r e v i r d e t a g r e p p u . t e f s o m r e p p u f o e t a g e h t o t n i p s i h t t c e n n o c e h t n e h w e n i m r e t e d o t y r t i u c r i c n o i t c e t o r p h g u o r h t - t o o h s e v i t p a d a e h t y b d e r o t i n o m s i n i p s i h t . f f o d e n r u t s a h t e f s o m r e p p u 2 22 t o o b y l p p u s p a r t s t o o b p a r t s t o o b e h t t c e n n o c . 2 l e n n a h c f o r e v i r d e t a g r e p p u g n i t a o l f e h t r o f c r o t i c a p a c t o o b . t i u c r i c p a r t s t o o b a m r o f o t n i p 2 w s e h t d n a n i p 2 t o o b n e e w t e b 3 2d i v . t u p n i d i v t e f s o m l a n r e t n i e h t n o s n r u t h g i h c i g o l . e g a t l o v e c n e r e f e r t s u j d a o t d e s u s i n i p s i h t . n i p t e s r o t d e t c e n n o c 4 2t e s r . g n i t t e s e g a t l o v e c n e r e f e r . h g i h = d i v n e h w w o l d e l l u p s i t a h t t u p t u o n i a r d n e p o n a s i n i p s i h t . e g a t l o v e c n e r e f e r e h t t e s o t n i p n i f e r o t n i p s i h t m o r f r o t s i s e r a t c e n n o c d a p d e s o p x e d n g . d n u o r g r e w o p i t n o i t c e n n o c e c n a d e p m i t s e w o l e h t h g u o r h t e n a l p / d n a l s i d n u o r g e h t o t n i p s i h t e . e l b a l i a v a functional pin descriptio n gate control logic pwm2 amplifier error oscillator pwm1 current balance vref boot1 hg1 sw1 lg1 boot2 hg2 sw2 lg2 reference voltage vcc refin pvcc internal regulator gate control logic por ss fbrtn eap fb comp csn csp psi vid rset iofs rt/en gnd power saving setting
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6210-ds-p0000 UP6210 5 preliminary the UP6210 is a compact dual-phase synchronous-rectified buck controller specifically designed to deliver high quality output voltage for high power applications. this part is capable of delivering up to 60a output current thanks to its embedded bootstrapped drivers that support 12v + 12v driving capability. the UP6210 features configurable gate driving voltage for maximum efficiency and optimal performance. the built-in bootstrap diode simplifies the circuit design and reduces external part count and pcb space. the output voltage is precisely regulated to the reference input that is dynamically adjustable by external voltage divider. the UP6210 adopts dcr current sensing technique for over current protection and droop control. the adjustable current balance is achieved by r ds(on) current sensing technique. this part features comprehensive protection functions including over current protection, input/output under voltage protection, over voltage protection and over temperature protection. other features include adjustable soft start, adjustable operation frequency, and quick response to step load transient. with aforementioned functions, this part provides customers a compact, high efficiency, well-protected and cost-effective solutions. this part comes to vqfn4x4-24l package. power on reset and initialization the UP6210 works with a single supply voltage at vcc pin. the vcc voltage is continuously monitored for power on reset (por) to ensure the supply voltage is high enough for normal operation of the device. the por threshold level is typically 9v at vcc rising. 9v ldo for gate drivers the UP6210 provides flexible gate driving voltage for maximum efficiency and optimal performance. a linear regulator provides 9v voltage at pvcc pin for gate drives. 9v driving voltage reduces the power dissipation at UP6210 to an acceptable level at large gate capacitance and high switching frequency applications. bootstrap diodes are embedded to facilitates pcb design and reduce the total bom cost. no external schottky diode is required. chip enable oscillation frequency programming a resistor r rt connected to rt pin programs the oscillation frequency as: ) k ( r 10000 f rt osc ? = (khz) functional description figure 1 shows the relationship between oscillation frequency and r rt . 10 100 1000 10 100 1000 r rt (kohm) switching frequency (khz) figure 1. switching frequency vs. r rt . when released, the rt/en pin voltage is regulated at 1v. pulling the rt/en pin to ground shuts down the UP6210. voltage control loop figure 2 shows the simplified voltage control loop of UP6210. vref is a reference voltage output with 1% accuracy and up to 1ma sourcing capability. rset is an open drain output that is controlled by vid pin. rset is pulled to fbrtn when vid = 1 and is set high impedance when vid = 0. therefore, the reference input voltage at refin pin is calculated as: 2 r 1 r 2 r v v ref refin + = for vid = 0 ) 3 r // 2 r ( 1 r 3 r // 2 r v v ref refin + = for vid = 1 users can control vid pin to get two reference voltage level. the current-limited buffer receives input at the vrefin pin and output a voltage source at ss pin. the output capability of the buffer is limited to 20ua during soft start and 200ua after soft start end. a capacitor c ss connected from ss to fbrtn sets the voltage slew rate. ua 20 c i c dt dv ss ss ss ss = = during soft start. ua 200 c i c dt dv ss ss ss ss = = after soft startend. these slew rate are used to control the output voltage slew at soft start and v refin jumping respectively.
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6210-ds-p0000 UP6210 6 preliminary functional description reference voltage ss vref refin UP6210 current limited buffer eap fb comp v out error amplifier i drp r drp fbrtn r1 r2 vid rset r3 figure 2. voltage control loop the fb voltage is tightly regulated to the positive input of the error amplifier, eap. the output current is sensed and mirrored to the eap pin, resulting in a voltage droop between ss and eap. drp drp ss eap i r v v ? = where i drp is a current signal proportional to output current. consequently, at steady state, the output voltage can be expressed as: drp drp ref out i r 2 r 1 r 2 r v v ? + = for vid = 0 drp drp ref out i r ) 3 r // 2 r ( 1 r 3 r // 2 r v v ? + = for vid = 1 soft start the UP6210 initiates its soft start cycle when the rt/en pin released from ground once the the por is granted as shown in figure 3. vid refin ss = eap v out rt/en figure 3. soft start cycle, r drp = 0 ? as mentioned in the above section, slew rate of voltage transition at ss and output voltage during soft start and v refin jumping is controlled by the capacitor connected to the ss pin. this reduces inrush current to charge/discharge the large output capacitors during soft start and vid changing. and prevents ocp, ovp/uvp false trigger. the ss buffer sinking/sourcing capability is limited to 20ua during soft start and 200ua after soft start end. therefore, the slew rate of voltage ramping up/down at ss, eap and fb pin during soft start or vid changing is calculated as: ss fb eap ss c ua 20 dt dv dt dv dt dv = = = during soft start. ss fb eap ss c ua 200 dt dv dt dv dt dv = = = after soft start. the UP6210 features pre-bias start-up capability. if the output voltage is pre-biased with a voltage, say v bias , that accordingly makes v fb higher than reference voltage ramping v eap . the error amplifier keeps v comp lower than the valley of the sawtooth waveform and makes pwm comparators output low until the ramping v eap catches up the feedback voltage. the UP6210 keeps both upper and lower mosfets off until the first pulse takes place. output current sensing figure 4 illustrates the output current sensing block of the UP6210. the voltage v cs across the current sensing capacitor c cs can be expressed as: v cs = i out x r dc / 2 if the following condition is true.
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6210-ds-p0000 UP6210 7 preliminary 2 x l / r dc = r csp x c cs where l is the output inductor of the buck converter, r dc is the parasitic resistance of the inductor, r csp and c cs are the external rc network for current sensing. the gm amplifier will source a current i csn to the csn pin to let its inputs virtually short circuit. i csn x r csn = v cs therefore the output current signal i csn can be expressed as: csn dc out csn r 2 r i i = the output current signal i csn is used as droop tuning, automatic phase reductin, and output over current protection. please see the related section for details. v out csp csn sw1 sw2 i csn UP6210 r csn c cs r dc r dc l l r csp r csp gm amplifer figure 4. output current sensing of UP6210. the sourcing capability of the gm amplifier is 100ua. it is recommended to scale i avg = 30ua at rated output current and set the ocp current as twice the rated output current. take a 60a converter for example. assume r dc = 2m ? , select the sense resistor according to ? = ? = k 2 ua 30 2 m 2 a 60 r csn over current protection the sensed current signals are monitored for over current protection. if i csn is higher than 60ua, the over current protection ocp is activated. take the above case for example, the ocp level is calculated as: a 120 m 2 k 2 ua 60 2 i ocp = ? ? = the ocp is of latch-off type and can be reset by toggling rt/en or vcc por. figure 5, and figure 6 illustrate the ocp behaviors during soft start and after soft start end respectively. current balance the UP6210 extracts phase currents for current balance by parasitic on-resistance of the lower switches when turned on as shown in figure 5. swx sample & hold current balance i cs1 i cs2 iofs UP6210 offset voltage figure 5. r ds(on) current sensing scheme the gm amplifier senses the voltage drop across the lower switch and converts it into current signal each time it turns on. the sampled and held current is expressed as: ua 6 . 6 10 r i i 3 ) on ( ds lx csx + = ? where i lx is the phase x current in ampere, r ds(on) is the on- resistance of low side mosfet in ? , 6.6ua is a constant to compensate the offset voltage of the current sensing circuit. the UP6210 fine tunes the duty cycle of each channel for current balance according to the sensed inductor current signals as shown in figure 6. if the current of channel 1 is smaller than the current of channel 2, the UP6210 increases the duty cycle of the corresponding phase to increase its phase current accordingly, vice verse. i cs2 i cs1 pwm1 pwm2 comp ramp1 ramp2 figure 6. current balance scheme of UP6210. functional description
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6210-ds-p0000 UP6210 8 preliminary functional description offset current tuning the UP6210 features an iofs pin for tuning the offset current between phase. the iofs pin voltage is nominal 0.5v when connecting a resistor to gnd and 1.5v when connecting a resistor to vref. connecting a resistor from iofs pin to gnd generate a current source as: ofs ofs r / v 5 . 0 i = this current is add to phase 1 current signal i cs1 for current balance. consequently, phase 2 will share more percentage of output current. connecting a resistor from iofs pin to vref generates a current source as: ofs ofs r / ) v 5 . 1 v 2 ( i ? = this current is add to phase 2 current signal i cs2 for current balance. consequently, phase 1 will share more percentage of output current. automatic phase reduction the UP6210 features automatic phase reduction that turns off phase 2 at light load condtion and reduces both switching and conduction losses. the automatic phase reduction maintains high power conversion efficiency over the output current range. the output current is sensed and mirrored to psi pin as: csn dc out csn psi r 2 r i i i = = the i psi creates a voltage v psi as: csn psi out psi psi psi r 2 r dcr i i r v = = the UP6210 operates in dual phase if v psi is higher than 0.6v and in single phase if v psi is lower than 0.4v. there is a 200mv hystersis at the phase change threshold. there is a 1ms delay when entering single phase operation and no time delay when entering dual phase operation. when operating single phase, both hg2 and lg2 are turned off. take the about case for example, with r psi = 80k ? , the threshold level of output current for entering single phase operation is calculated as: a 10 i k 80 m 2 k 2 2 v 4 . 0 i r 2 r dcr i v 4 . 0 out out csn psi out = ? ? ? = = the threshold level of output current for entering dual phase operation is calculated as: a 15 i k 80 m 2 k 2 2 v 6 . 0 i r 2 r dcr i v 6 . 0 out out csn psi out = ? ? ? = = note that when operated in single phase, the rated current is reduced to 80 percents of normal level. continuous demanding high current may damage the converter. connect psi pin to vref to disable the automatic phase reduction function. since the vref has no sinking capability, make sure the external loading is higher than 100ua when connecting psi pin to vref. otherwise, vref may loss its regulation. over voltage and under voltage protection the fb voltage is continuously monitored for over voltage and under voltage protection. the UP6210 asserts over voltage protection if v fb > v ss + 300mv and turns on the lower mosfets and shuts down the converter. the UP6210 asserts under voltage protection if v fb < v ss - 300mv and shuts down the converter. the uvp function is disabled during soft start. both uvp and ovp are latch-off type and can be reset only by toggling the rt/en pin ro by vcc power on reset.
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6210-ds-p0000 UP6210 9 preliminary r e t e m a r a pl o b m y ss n o i t i d n o c t s e tn i mp y tx a ms t i n u t u p n i y l p p u s e g a t l o v y l p p u sv 2 1 c c 5 . 4- -2 . 3 1v t n e r r u c y l p p u si c c v ; n e p o g l d n a g h c c , v 2 1 = g n i h c t i w s - -5- -a m t n e r r u c y l p p u s t n e c s e i u qi q _ c c i , g n i h c t i w s o n c c p a m 0 =- -4- -a m e g a t l o v y l p p u s d e t a l u g e rv c c p i , v 0 = n e / t r c c p a m 0 =890 1v d l o h s e r h t r o pv h t r c c 89 0 1v s i s e r e t s y h r o pv s y h c c - -0 . 1- -v g n i t t e s y c n e u q e r f / e l b a n e p i h c t n e r r u c g n i c r u o s n e / t ri n e / t r . d n g = n e / t r0 0 10 5 10 0 2a u e g a t l o v n e / t rv n e / t r r n e / t r k 3 3 = ? - -1- -v e g n a r g n i t t e s y c n e u q e r f g n i h c t i w s 0 5- -0 0 0 1z h k y c n e u q e r f g n i h c t i w s n u r e e r ff c s o r n e / t r k 3 3 = ? 0 7 20 0 30 3 3z h k y c a r u c c a y c n e u q e r f g n i h c t i w s ? f c s o f c s o z h k 0 0 5 ~ z h k 0 0 2 =5 1 -- -5 1% supply input voltage, vcc (note 1) --------------------------------------------------------------------------------------------- -0.3v to +15v sw to gnd dc ---------------------------------------------------------------------------------------------------------------------------- --------- -0.3v to 15v < 200ns ----------------------------------------------------------------------------------------------------------------------- ----- -5v to 30v boot to sw -------------------------------------------------------------------------------------------------------------------- ------------------ 15v boot to gnd dc ------------------------------------------------------------------------------------------------------------------------- -0 .3v to phase +15v < 200ns ----------------------------------------------------------------------------------------------------------------------- --- -0.3v to 42v input, output or i/o voltage -------------------------------------------------------------------------------------------------- -------- -0.3v to +6v storage temperature range ------------------------------------------------------------------------------------------------------------- -65 o c to +150 o c junction temperature ------------------------------------------------------------------------------------------------------------------------------- ----- 150 o c lead temperature (soldering, 10 sec) ------------------------------------------------------------------------------------------------------------ 260 o c esd rating (note 2) hbm (human body mode) --------------------------------------------------------------------------------------------------------------------- 2kv mm (machine mode) ----------------------------------------------------------------------------------------------------------------------------- 2 00v package thermal resistance (note 3) vqfn4x4-24l ja ------------------------------------------------------------------------------------------------------------------------- 40 c/w power dissipation, p d @ t a = 25 c vqfn4x4-24l ------------------------------------------------------------------------------------------------------------------- --------------------- 2.5w operating junction temperature range (note 4) ------------------------------------------------------------------------ -40 c to +125 c operating ambient temperature ra nge -------------------------------------------------------------------------------------- -40 c to +85 c supply input voltage, v cc -------------------------------------------------------------------------------------------------------- 10.8v to 13.2v a bsolute maximum ratin g thermal informatio n recommended operation conditions electrical characteristics (v cc = 12v, t a = 25 o c, unless otherwise specified)
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6210-ds-p0000 UP6210 10 preliminary electrical characteristics r e t e m a r a pl o b m y ss n o i t i d n o c t s e tn i mp y tx a ms t i n u t r a t s t f o s t n e r r u c t r a t s t f o si s s . t r a t s t f o s g n i r u d- -0 2- - a u t n e r r u c y l p p u si c c . d n e t r a t s t f o s r e t f a- -0 0 2- - r o t a l l i c s o e l c y c y t u d m u m i x a m - -5 8- -% e l c y c y t u d m u m i x a m - -0- -% e d u t i l p m a p m a r ? v c s o v c c . v 2 1 =- -5 . 3- -v e d o m g n i v a s r e w o p l a u d g n i r e t n e r o f e g a t l o v d l o h s e r h t e s a h p v i s p v i s p . g n i s i r5 5 . 06 . 05 6 . 0v g n i r e t n e r o f e g a t l o v s i s e r e t s y h e s a h p e l g n i s ? v i s p v i s p . g n i l l a f- -0 0 2- -v m e g a t l o v e c n e r e f e r y c a r u c c a e g a t l o v e c n e r e f e rv f e r i f e r a u 0 0 1 =8 9 . 10 0 . 22 0 . 2v n o i t a l u g e r d a o l e g a t l o v e c n e r e f e r ? v f e r i f e r a m 2 ~ 0 =5 -- -5v m y c a r u c c a e g a t l o v t u p t u ov b f v | n i f e r v - b f v , | c c , d a o l o n , v 2 1 = r p r d 0 = ? v , n i f e r . v 6 . 1 ~ v 8 . 0 = - -- -5v m r e i f i l p m a r o r r e n i a g c d p o o l n e p oo a. n g i s e d y b d e e t n a r a u g0 70 8- -b d t c u d o r p h t d i w d n a b - n i a gw b gc d a o l . n g i s e d y b d e e t n a r a u g , f p 5 =0 2- -- -z h m e t a r w e l sr s. n g i s e d y b d e e t n a r a u g5 10 2- -s u / v ) e c r u o s & k n i s ( t n e r r u c m u m i x a mi p m o c v p m o c v 6 . 1 =5 . 10 . 2- -a m e s n e s t n e r r u c l a t o t t n e r r u c g n i c r u o s m u m i x a mi x a m _ n s c 0 0 1- -- -a u t e s f f o r e i f i l p m a m g 1 -01v m d l o h s e r h t n o i t c e t o r p t n e r r u c r e v o l e v e l i p c o _ n s c - -0 6- -a u y c a r u c c a p o o r di p r d i / n s c 0 90 0 10 1 1% y c a r u c c a i s pi i s p i / n s c 0 90 0 10 1 1% e s n e s t n e r r u c e s a h p e c n a t c u d n o c - s n a r t - -0 . 1- -s m e g a t l o v s f o i v s f o k 0 0 1 ? f e r v o t s f o i m o r f- -5 . 1- - v k 0 0 1 ? d n g o t s f o i m o r f- -5 . 0- -
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6210-ds-p0000 UP6210 11 preliminary r e t e m a r a pl o b m y ss n o i t i d n o c t s e tn i mp y tx a ms t i n u t u p n i l o r t n o c d i v l e v e l d l o h s e r h t h g i h c i g o lv l i 2 . 1- -- -v l e v e l d l o h s e r h t w o l c i g o lv l i - -- -4 . 0v t e f s o m t e s r f o e c n a r t s i s e r n or t e s r h g i h = d i v- -0 2- - ? n i p t e s r f o e g a k a e li t e s r v t e s e r v 0 = d i v , v 2 =- -- -1 . 0a u r e v i r d e t a g g n i c r u o s e t a g r e p p ur c r s _ g h i g h g n i c r u o s a m 0 0 1 =- -24 ? g n i k n i s e t a g r e p p ur k n s _ g h i g h g n i k n i s a m 0 0 1 =- -5 . 13 ? e c r u o s e t a g r e w o lr c r s _ g l i g l g n i c r u o s a m 0 0 1 =- -24 ? k n i s e t a g r e w o lr k n s _ g l i g l g n i k g n i s a m 0 0 1 =- -12 ? e m i t d a e dt t d - -0 3- -s n n o i t c e t o r p n o i t c e t o r p e g a t l o v r e v ov b f v - s s - -0 0 3- -v m n o i t c e t o r p e g a t l o v r e d n uv b f v - s s - -0 0 3 -- -v m n o i t c e t o r p e r u t a r e p m e t r e v o - -0 5 1- - o c s i s e r e t s y h e r u t a r e p m e t r e v o - -0 2- - o c note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution recommended. note 3. ja is measured in the natural convection at t a = 25 c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard. note 4. the device is not guaranteed to function outside its operating conditions. electrical characteristics
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6210-ds-p0000 UP6210 12 preliminary typical operation characteristics ph1 (10v/div) rt/en (1v/div) ss (1v/div) v out (1v/div) ph1 (10v/div) rt/en (1v/div) ss (1v/div) v out (1v/div) ph1 (10v/div) rt/en (1v/div) ss (1v/div) v out (1v/div) ph1 (10v/div) rt/en (1v/div) ss (1v/div) v out (1v/div) ug1 ( 5v/div) lg1 (5v/div) ph1 (5v/div) ug1 ( 5v/div) lg1 (5v/div) ph1 (5v/div) power off waveforms time (200us/div) v in = 12v, i out = 40a power on waveforms time (2ms/div) v in = 12v, i out = 40a turn on waveforms time (200us/div) v in = 12v, i out = 40a output voltage load regulation time (100us/div) v in = 12v, i out = 40a ug1 falling waveforms time (40ns/div) v in = 12v, i out = 40a, 20mhz bandwidth limited ug1 rising waveforms time (40ns/div) v in = 12v, i out = 40a, 20mhz bandwidth limited
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6210-ds-p0000 UP6210 13 preliminary 1.95 1.96 1.97 1.98 1.99 2 2.01 2.02 2.03 2.04 2.05 6 7 8 9 10 11 12 13 14 typical operation characteristics fb (1v/div) lg1 (10v/div) ph1 (10v/div) psi (1v/div) ph2 (10v/div) ph1 (10v/div) v out (1v/div) psi (1v/div) ph2 (10v/div) ph1 (10v/div) power off waveforms time (20us/div) over voltage protection time (2us/div) turn on waveforms time (2ms/div) v in = 12v, i out = 0a to 40a 4 5 6 7 8 9 10 11 67891011121314 vcc9 line regulation input voltage (v) vcc9 voltage (v) vref load regulation loading current (ma) vref variation (%) -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0 5 10 15 20 vref line regulation input voltage (v) vref voltage (v)
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6210-ds-p0000 UP6210 14 preliminary 290 292 294 296 298 300 302 304 306 308 310 -50 -25 0 25 50 75 100 125 1.95 1.96 1.97 1.98 1.99 2 2.01 2.02 2.03 2.04 2.05 -50-25 0 25 50 75100125 100 1000 110100 typical operation characteristics frequency vs. rt rt (k ? ) frequency (khz) efficiency vs. output current with auto psi output current (a) efficiency (%) vcc9 voltage vs. tempereture junction temperature ( o c) vcc9 voltage (v) vref voltage vs. temperature junction temperature ( o c) vref voltage (v) 40 50 60 70 80 90 100 0 10203040506070 1 phase operation 2 phase operation 9.27 9.28 9.29 9.3 9.31 9.32 9.33 -50 -25 0 25 50 75 100 125 switching frequency vs. tempereture junction temperature ( o c) switching frequency (khz)
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6210-ds-p0000 UP6210 15 preliminary a pplication information fbrtn configuration since the reference voltage v ref is measured with respective to fbrtn, connect circuits related to vref, refin, and ss pin to fbrtn locally with short traces as shown in the typical application circuit . total current sensing in the real application, pcb trances are not ideal and have certain parasitic resistances r pcb1 and r pcb2 as shown in figure 1. when these parasistic resistances are not identical, the voltages at inductor terminals are not the same, contributing meausrement error on total current sensing. two 1 ? resistors, connecting directly to inductor terminals are recommended to elimiate the effects of parasitic resistance. a 0.1uf capacitor c byp is also recommended to bypassing noise when the UP6210 is far away from the output inductors. place the c byp physically near the ic. v out csp csn sw1 sw2 i csn UP6210 r csn c cs r dc l l r csp r csp gm amplifer r dc r pcb1 r pcb2 1ohm 1ohm c byp figure 1. parasitic resistance of pcb
upi semiconductor corp., http://www.upi-semi.com rev. p00, file name: UP6210-ds-p0000 UP6210 16 preliminary package information note 1.package outline unit description: bsc: basic. represents theoretical exact dimension or dimension target min: minimum dimension specified. max: maximum dimension specified. ref: reference. represents dimension for reference use only. this value is not a device specification. typ. typical. provided as a general value. this value is not a device specification. 2.dimensions in millimeters. 3.drawing not to scale. 4.these dimensions do not include mold flash or protrusions. mold flash or protrusions shell not exceed 0.15mm. 3.90 - 4.10 pin 1 mark (note 6) bottom view - exposed pad 2.65 - 2.75 2.30 - 2.75 0.18 - 0.30 2.30 - 2.75 0.35 - 0.45 3.10 - 3.20 4.50 - 4.70 3.90 - 4.10 0.0 - 0.05 0.80 - 1.00 0.20 bsc recommended solder pad pitch and dimensions 0.20 - 0.30

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